In integrated circuits, chemical mechanical polishing (CMP) has been used to planarize interlayer dielectrics; however, CMP processes are sensitive to layout patterns, and this can cause certain regions on chip to have thicker dielectric layers than other regions due to differences in the underlying topography.
Metal fill usage is a common process requirement for manufacturing in integrated circuits. Metal fill has been found to be one of the most commercially viable options in reducing layout dependent dielectric thickness variation. Also, metal fill is used to meet design rules, which are required by foundries for processing of the integrated circuit. For example, physical design tools insert dummy metal patterns, e.g., metal fill, so that designs meet the required metal density as specified by foundries to reduce the thickness variation. More specifically, metal-fill patterning is the process of filling large open areas on each metal layer with a floating metal pattern to compensate for pattern-driven variations.
However, metal fill adds parasitic capacitance to the integrated circuit with more than 10% capacitance increase for a single interconnect. This is due to the fact that the metal fills effectively decrease the spacing between features. Due to the increase in capacitance, the designer may need to redesign the integrated circuit to compensate for the parasitic capacitance. This design process is an iterative process of (i) circuit schematic design, (ii) add metal fill in the layout, (iii) determine effect of metal fill on the circuit, (iv) adjust metal fill and circuit schematic design, (v) determine effect on circuit, etc, which is time consuming and expensive.
Foundries use automatic metal fill algorithms to insert dummy fills (metal fills) in the design where metal is sparsely distributed. However, these fill algorithms do not take into consideration the design parameters, e.g., functionality of the integrated circuit, when providing the dummy fills. And, physical verification tools can be effectively used in inserting such dummy metal fills based on certain criteria. Parasitic extraction tools, though, can be used to evaluate the effect of the metal fill. However, parasitic extraction can only be performed after layout, which is the last step in the circuit design flow. As the parasitic extraction can only be performed after layout, the designer will have to redesign the integrated circuit to compensate for the parasitic capacitance, at a very late stage in the circuit flow design. This means that the designer, after the expenditure of considerable time and expense, will have to start the design process at the beginning of the circuit flow design and then reevaluate the metal fill effects on the new design.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.